CMOS

Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry metal–oxide–semiconductor (COS-MOS), is a type of (metal–oxide–semiconductor field-effect transistor)  that uses complementary and symmetrical pairs of  and  MOSFETs for logic functions. CMOS technology is used for constructing (IC) chips, including s, s, s (including ), and other  circuits. CMOS technology is also used for s such as s (s),, s , and highly integrated s for many types of communication.

and invented the MOSFET at  in 1959, and then demonstrated the  (p-type MOS) and  (n-type MOS) fabrication processes in 1960. These processes were later combined and adapted into the complementary MOS (CMOS) process by and  at  in 1963. commercialized the technology with the trademark "COS-MOS" in the late 1960s, forcing other manufacturers to find another name, leading to "CMOS" becoming the standard name for the technology by the early 1970s. CMOS eventually overtook NMOS as the dominant MOSFET fabrication process for (VLSI) chips in the 1980s, and has since remained the standard fabrication process for MOSFET s in VLSI chips. , 99% of IC chips, including most and s, are fabricated using CMOS technology.

Two important characteristics of CMOS devices are high and low static. Since one of the MOSFET pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much as other forms of logic, like  or  (TTL), which normally have some standing current even when not changing state. These characteristics allow CMOS to integrate a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most widely used technology to be implemented in VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of MOS s, having a electrode placed on top of an oxide insulator, which in turn is on top of a. was once used but now the material is. Other metal gates have made a comeback with the advent of dielectric materials in the CMOS process, as announced by IBM and Intel for the  node and smaller sizes.

Technical details
"CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates than  with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes. CMOS logic consumes over times less power than, and about 100,000 times less power than bipolar (TTL).

CMOS circuits use a combination of p-type and n-type (MOSFETs) to implement s and other digital circuits. Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece of of between 10 and 400 mm2.

CMOS always uses all MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).

History
The (metal-oxide-semiconductor field-effect transistor, or MOS transistor) was invented by  and  at  in 1959. There were originally two types of MOSFET, ( MOS) and  ( MOS). Both types were developed by Atalla and Kahng when they originally invented the MOSFET, fabricating both PMOS and NMOS devices with a in 1960. While the MOSFET was initially overlooked and ignored by Bell Labs in favour of, the MOSFET invention generated significant interest at. Base on Atalla's work, introduced MOS technology to Fairchild with his MOS-controlled  fabricated in late 1960.

A new type of MOSFET logic combining both the PMOS and NMOS processes was developed, called complementary MOS (CMOS), by Chih-Tang Sah and at Fairchild. In February 1963, they published the invention in a. Wanlass later filed for CMOS circuitry in June 1963, and it was granted in 1967. In both the research paper and the, the fabrication of CMOS devices was outlined, on the basis of of a silicon substrate to yield a layer of  located between the drain contact and the source contact.

CMOS was commercialised by in the late 1960s. RCA adopted CMOS for the design of s (ICs), developing CMOS circuits for an computer in 1965 and then a 288- CMOS  memory chip in 1968. RCA also used CMOS for its in 1968, starting with a 20  before gradually scaling to a  over the next several years.

CMOS technology was initially overlooked by the American in favour of NMOS, which was more powerful at the time. However, CMOS was quickly adopted and further advanced by Japanese semiconductor manufacturers due to its low power consumption, leading to the rise of the Japanese semiconductor industry. developed C²MOS (Clocked CMOS), a circuit technology with lower and faster operating speed than ordinary CMOS, in 1969. Toshiba used its C²MOS technology to develop a (LSI) chip for 's Elsi Mini , developed in 1971 and released in 1972. (now ) began developing a CMOS IC chip for a  in 1969, and began mass-production with the launch of the  Analog Quartz 38SQW watch in 1971. The first mass-produced CMOS consumer electronic product was the Pulsar "Wrist Computer" digital watch, released in 1970. Due to low power consumption, CMOS logic has been widely used for and  since the 1970s.

The in the early 1970s were PMOS processors, which initially dominated the early  industry. By the late 1970s, NMOS microprocessors had overtaken PMOS processors. CMOS microprocessors were introduced in 1975, with the, and RCA. However, CMOS processors did not become dominant until the 1980s.

CMOS was initially slower than, thus NMOS was more widely used for computers in the 1970s. The 5101 (1 ) CMOS memory chip (1974) had an  of 800, whereas the fastest NMOS chip at the time, the Intel 2147 (4kb SRAM)  memory chip (1976), had an access time of 55/70ns. In 1978, a research team led by Toshiaki Masuhara introduced the twin-well Hi-CMOS process, with its HM6147 (4kb SRAM) memory chip, manufactured with a. The Hitachi HM6147 chip was able to match the performance (55/70ns access) of the Intel 2147 HMOS chip, while the HM6147 also consumed significantly less power (15) than the 2147 (110mA). With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common for computers in the 1980s.

In the 1980s, CMOS microprocessors overtook NMOS microprocessors. 's spacecraft, sent to orbit  in 1989, used the  CMOS microprocessor due to low power consumption.

Intel introduced a for CMOS  in 1983. In the mid-1980s, of  developed high-performance, low-voltage,  CMOS technology, which enabled the development of faster computers as well as  and battery-powered. In 1988, Davari led an IBM team that demonstrated a high-performance CMOS process.

commercialized a 700 CMOS process in 1987, and then Hitachi,, and Toshiba commercialized  CMOS in 1989. In 1993, commercialized a  CMOS process, while Hitachi and NEC commercialized  CMOS. Hitachi introduced a CMOS process in 1995, then Mitsubishi introduced 150nm CMOS in 1996, and then  introduced 140nm in 1999.

In 2000, and Trung T. Doan at  invented  , leading to the development of a cost-effective  CMOS process. Toshiba and Sony developed a CMOS process in 2002, and then  initiated the development of  CMOS logic in 2004. The development of pitch by Gurtej Singh Sandhu at Micron Technology led to the development of  class CMOS in the 2000s.

CMOS is used in most modern LSI and devices. As of 2010, with the best  each year have been CMOS  since 1976. As of 2019, planar CMOS technology is still the most common form of semiconductor device fabrication, but is gradually being replaced by non-planar technology, which is capable of manufacturing s smaller than.

Inversion
CMOS circuits are constructed in such a way that all (PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low between its source and drain contacts when a low gate  is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.

The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output, therefore, registers a high voltage.

On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output from drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.

Power supply pins
The power supply pins for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on the manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the drain and source supplies. These do not apply directly to CMOS, since both supplies are really source supplies. VCC and Ground are carryovers from and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.

Duality
An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

Logic
More complex logic functions such as those involving and s require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is a of a  in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a (NOT AND) logic gate.

An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See for a method of calculating delay in a CMOS circuit.

Example: NAND gate in physical layout
This example shows a logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a substrate. The, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the (illustrated in green color) are in polysilicon. The transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate while the P device is manufactured in an well (n-well). A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent.

Power: switching and leakage
CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical in a modern  process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from Vdd to Vss through the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:

Static dissipation
Both NMOS and PMOS transistors have a gate–source, below which the current (called sub threshold current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V, and Vth for both NMOS and PMOS might have been 700 mV). A special type of the transistor used in some CMOS circuits is the, with near zero.

SiO2 is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130 nm technology with gate oxides of 20 Å or thinner.

Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily.

Charging and discharging of load capacitances
CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from VDD to the load capacitance to charge it and then flows from the charged load capacitance (CL) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=CLVDD is thus transferred from VDD to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device: $$ P = 0.5 C V^2 f $$.

Since most gates do not operate/switch at every, they are often accompanied by a factor $$\alpha$$, called the activity factor. Now, the dynamic power dissipation may be re-written as $$ P = \alpha C V^2 f $$.

A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1. If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from VDD to ground, hence creating a. Short-circuit power dissipation increases with rise and fall time of the transistors.

An additional form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS logic networks are partially conductive, and current flows directly from VDD to VSS. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires ameliorates this effect, but crowbar power can be a substantial part of dynamic CMOS power.

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a Vth of 200 mV has a significant current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high Vth transistors are used when switching speed is not critical, while low Vth transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional component because of current  through the extremely thin gate dielectric. Using s instead of that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.

Input protection
Parasitic transistors that are inherent in the CMOS structure may be turned on by input signals outside the normal operating range, e.g. s or. The resulting may damage or destroy the CMOS device. Clamp diodes are included in CMOS circuits to deal with these signals. Manufacturers' data sheets specify the maximum permitted current that may flow through the diodes.

Analog CMOS
Besides digital applications, CMOS technology is also used in applications. For example, there are CMOS ICs available in the market. s may be used as analog instead of signal s. CMOS technology is also widely used for  circuits all the way to microwave frequencies, in  (analog+digital) applications.

RF CMOS
RF CMOS refers to s ( circuits) which are based on  technology. They are widely used in  technology. RF CMOS was developed by while working at  in the late 1980s. This changed the way in which RF circuits were designed, leading to the replacement of discrete with CMOS integrated circuits in. It enabled sophisticated, low-cost and portable terminals, and gave rise to small, low-cost, low-power and portable units for a wide range of wireless communication systems. This enabled "anytime, anywhere" communication and helped bring about the, leading to the rapid growth of the wireless industry.

The s and radio transceivers in all modern devices and  are mass-produced using RF CMOS devices. RF CMOS circuits are widely used to transmit and receive wireless signals, in a variety of applications, such as technology (such as ),, ,  (NFC), s (such as  and ),  , and   applications, among other uses.

Examples of commercial RF CMOS chips include Intel's cordless phone, and   chips created by  and other companies. Commercial RF CMOS products are also used for and  (WLAN) networks. RF CMOS is also used in the radio transceivers for wireless standards such as, Wi-Fi, and Bluetooth, transceivers for mobile networks such as 3G, and remote units in s (WSN).

RF CMOS technology is crucial to modern wireless communications, including wireless networks and devices. One of the companies that commercialized RF CMOS technology was. Its bulk CMOS sell over 1billion units annually, reaching a cumulative 5billion units,.

Temperature range
Conventional CMOS devices work over a range of –55 °C to +125 °C.

There were theoretical indications as early as August 2008 that silicon CMOS will work down to –233 °C (40 ). Functioning temperatures near 40 K have since been achieved using overclocked AMD processors with a combination of liquid nitrogen and liquid helium cooling.

Single-electron MOS transistors
Ultra small (L = 20 nm, W = 20 nm) MOSFETs achieve the single-electron limit when operated at cryogenic temperature over a range of –269 °C (4 ) to about –258 °C (15 ). The transistor displays due to progressive charging of electrons one by one. The number of electrons confined in the channel is driven by the gate voltage, starting from an occupation of zero electrons, and it can be set to one or many.